(a) Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a liquid crystal display having a dual shift clock wire.
(b) Description of the Related Art
FIG. 1 shows a block diagram of a conventional thin film transistor liquid crystal display TFT-LCD. The conventional TFT-LCD includes an LCD panel 10, a data driver 20, a gate driver 30 and a timing controller 40. A plurality of gate lines (not shown), or scanning lines, are formed in parallel on the LCD panel 10, and a plurality of data lines (not shown) perpendicularly intersect the gate lines insulated from the gate lines. Further, pixel electrodes are formed at the intersection of data lines and the gate lines. A thin film transistor (TFT), which acts as a switching device, is formed at each of the pixels. A thin film transistor (TFT), which acts as a switching device, is formed at each of the pixels. A gate electrode, a source electrode and a drain electrode of the TFT is respectively connected to a gate line a data line and a pixel electrode.
The data driver 20 is electrically connected to the data lines of the LCD panel 10. After receiving digital signals of R, G, B data and control signals from the timing controller 40, the data driver 20 outputs corresponding R, G, B data voltages, which are analog signals, to each data line of the LCD panel 10. If the data driver 20 is designed in a single integrated circuit to connect the data lines, the integrated circuit chip needs a large number of output pins. Therefore, the data driver 20 is comprised of a plurality of data driver ICs 20a, 20b, 20c and 20d connected to the data lines.
The gate driver 30 is electrically connected to the gate lines of the LCD panel 10 and applies voltages successively to the gate lines to turn on the TFTs. If a TFT connected to one of the gate lines is turned on by the gate voltage, the data voltages applied to the data lines are transmitted to the pixel electrodes through the drain electrodes of the TFTs. Like the data driver 20, the gate driver 30 is also comprised of a plurality of gate driver ICs 30a, 30b, 30c and 30d. 
The timing controller 40 outputs R, G, B data signals to the data driver 20 and various timing signals to the data driver 20 as well as to the gate driver 30. The timing controller 40 is provided on a printed circuit board PCB 50 separated from the data driver 20 and the gate driver 30. Further, various timing signals and R, G, B data signals from the timing controller 40 are transmitted to the data driver 20 and the gate driver 30 through wires formed on the PCB 50. Among the signals from the timing controller 40 to the data driver 20 are data signals and a shift clock signal for storing the data signals in a shift register (not shown) of the data driver 20.
Since the frequency of the shift clock signal exceeds 65 MHz in an XGA-class TFT-LCD, electromagnetic interference (EMI) occurs when the shift clock signal is transmitted to the data driver ICs 20a, 20b, 20c and 20d through the wires of the PCB 50. This is compounded by the fact that the wires of the timing controller 40 transmitting the shift clock signal must be long enough to connect each of the data driver ICs 20a, 20b, 20c and 20d located along the length of the data driver 20 connecting the data lines of the LCD panel 10 (lengths of the LCD panel 10, the data driver 20 and the PCB 50 are substantially identical). That is, the clock signal is transmitted through an extensive distance, causing an increased generation of EMI.